Design for Testability - DFT Training Provided by Maven Silicon Softech Pvt Ltd Training Institute in Bangalore
Design for Testability DFT free videos and free material uploaded by Maven Silicon Softech Pvt Ltd Training Institute staff .
1:Reference Books
Lecture 1DFT Theory - Reference
Book
Lecture 2Tessent Shell
2:Intro to Testing
Lecture 3Introduction to Testing
and DFT
Lecture 4Verification vs Testing
Lecture 5Faults and Types of
Testing
Lecture 6Levels of Testing
Lecture 7Fault Modelling
3:Fault Collapsing
Lecture 8Fault Collapsing (Part-1)
Lecture 9Fault Collapsing (Part-2)
Lecture 10Fault Collapsing
(Part-3)
4:Introduction to ATPG
Lecture 11Introduction to ATPG
Lecture 12Combinational ATPG
Lecture 13D-Algorithm
5:Fault Classes and Fault Simulation
Lecture 14Fault Classes
Lecture 15Additional Fault Models
(part-1)
Lecture 16Additional Fault Models
(part-2)
Lecture 17Fault Simulation
6:DFT - Basics
Lecture 18What is DFT?
Lecture 19Classification of DFT
Techniques
Lecture 20Structured DFT
Techniques
7:Scan Insertion & Test Compression
Lecture 21Scan Insertion (Part -
1)
Lecture 22Scan Insertion (Part -
2)
Lecture 23Scan Insertion (Part -
3)
Lecture 24Scan Insertion (Part -
4)
Lecture 25Hierachical DFT Flow
Lecture 26Test Compression
8:Boundary Scan & BIST
Lecture 27Boundary Scan
Lecture 28JTAG vs IJTAG
Lecture 29Introduction to BIST,
LBIST & MBIST
9:Miscellaneous Concepts
Lecture 30Design Rule Checks
Lecture 31How to improve Test
Coverage
Lecture 32Fault Diagnosis
10:Tessent Shell Overview
Lecture 33Intro to Tessent
Lecture 34System Modes
Lecture 35TSDB Overview
11:DFT - Labs
Lecture 36DFT - Lab Manual
Lecture 37Solution to Lab 01
Lecture 38Solution to Lab 02
Lecture 39Solution to Lab 03
Lecture 40Solution to Lab 04
Lecture 41Solution to Lab 05
Lecture 42Solution to Lab 06
Lecture 43Solution to Lab 07
Lecture 44Solution to Lab 08
Lecture 45Solution to Lab 09
Lecture 46Solution to Lab 10
Lecture 47Solution to Lab 11
Lecture 48Solution to Lab 12
Lecture 49Solution to Lab 13
Lecture 50Solution to Lab 14
Lecture 51Solution to Lab 15
Design For Testability is one of the essential processes in VLSI Design Flow. It is intended to detect the manufacturing defects in a fabricated chip since the fabrication process's yield is never 100%. DFT methodology offers various techniques to increase the efficiency of the silicon testing process of a fabricated chip. This DFT Training course will cover the necessary basics of silicon testing, the importance of testing, and different DFT techniques such as SCAN Insertion, ATPG, JTAG, and BIST.
Also, this course will give the learners a hands-on experience of the
implementation of all DFT techniques using the industry-standard tool Tessent
from Mentor Graphics.
Write a public review