RISC-V RV32I RTL Design free videos and free material uploaded by Maven Silicon Softech Pvt Ltd Training Institute staff .
1: RISC-V RV32I Reference Guide
Lecture 1 RISC-V
RV32I Quick Reference Guide
2: RISC-V RV32I RTL Architecture Design
Lecture 2 RISC-V
Execution Stages and Flow
Lecture 3 RISC-V
Register File and RV32I Instructions Format
Lecture 4 RV32I
– R Type ALU Datapath
Lecture 5 RV32I
– I Type ALU Datapath
Lecture 6 RV32I
– S Type ALU Datapath - Load & Store
Lecture 7 RV32I
– B Type ALU Datapath
Lecture 8 RV32I
– J Type ALU Datapath – JAL & JALR
Lecture 9 RV32I
– U Type ALU Datapath and Summary
Quiz 1 Knowledge
Check - RISC-V RTL Architecture Design
3: RISC-V RV32I 5 Stage Pipelined RTL
Design
Lecture 10 CPU
Performance and RISC-V 5 Stage Pipeline Overview
Lecture 11 RISC-V
5 Stage Pipeline – Data Hazards & Design Approach
Lecture 12 RISC-V
5 Stage Pipeline – Control Hazards & Design Approach
Quiz 2 Knowledge
Check - RISC-V RV32I 5 Stage Pipelined RTL Design
This RISC-V RTL Design course explains the complete RTL
design process, how you can create a basic architecture for J-type instructions
initially and scale up the same sequentially in phases to implement all other
RV 32 I instructions. In this course, you will explore how you can create a
processor using all the basic building blocks like register, memory, adder, multiplexer,
ALU, decoder and control logic like FSMs.
Also, it explains why CPU performance is very essential and
how to improve CPU performance through a pipeline design methodology. In this
course, you will explore how to implement a five-stage pipelined RISC-V
processor.
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