RISC-V RV32I RTL Design using Verilog HDL

1:RISC-V Instruction Set Architecture

Lecture 1             Why RISC-V Processor?

Lecture 2             RISC-V processor overview

Lecture 3             RISC-V ISA Overview

Lecture 4             RV32I – R Type Instruction

Lecture 5             RV32I – I Type Instruction

Lecture 6             RV32I – S and B Type Instructions

Lecture 7             RV32I – J and U Type Instructions

Lecture 8             RV32I – Assembly Programs and Summary

Quiz 1    Knowledge Check - RISC-V Instruction Set Architecture

2:RISC-V RV32I Reference Guide

Lecture 9             RISC-V RV32I Quick Reference Guide

3:RISC-V RV32I RTL Architecture Design

Lecture 10           RISC-V Execution Stages and Flow

Lecture 11           RISC-V Register File and RV32I Instructions Format

Lecture 12           RV32I – R Type ALU Datapath

Lecture 13           RV32I – I Type ALU Datapath

Lecture 14           RV32I – S Type ALU Datapath - Load & Store

Lecture 15           RV32I – B Type ALU Datapath

Lecture 16           RV32I – J Type ALU Datapath – JAL & JALR

Lecture 17           RV32I – U Type ALU Datapath and Summary

Quiz 2    Knowledge Check - RISC-V RTL Architecture Design

4:RISC-V RV32I 5 Stage Pipelined RTL Design

Lecture 18           CPU Performance and RISC-V 5 Stage Pipeline Overview

Lecture 19           RISC-V 5 Stage Pipeline – Data Hazards & Design Approach

Lecture 20           RISC-V 5 Stage Pipeline – Control Hazards & Design Approach

Quiz 3    Knowledge Check - RISC-V RV32I 5 Stage Pipelined RTL Design

5:Verilog HDL

Lecture 21           Setting Expectations - Course Agenda

Lecture 22           Introduction to Verilog HDL

Quiz 4    Knowledge Check - Introduction to Verilog HDL

6:Verilog HDL Reference Guide

Lecture 23           Verilog HDL - Quick Reference Guide

7:Verilog HDL: Data Types

Lecture 24           Data Types

Quiz 5    Knowledge Check - Data Types

8:Verilog HDL: Operators

Lecture 25           Verilog Operators

Quiz 6    Knowledge Check - Verilog Operators

9:Advanced Verilog for Verification

Lecture 26           Advance Verilog for Verification

Quiz 7    Knowledge Check - Advanced Verilog for Verification

10:Verilog HDL: Assignments

Lecture 27           Assignments

Quiz 8    Knowledge Check - Assignments

11:Verilog HDL: Structured Procedures

Lecture 28           Structured Procedures

Quiz 9    Knowledge Check - Structured Procedures

12:Verilog HDL : Synthesis Coding Style

Lecture 29           Synthesis Coding Style

Quiz 10 Knowledge Check - Synthesis Coding Style

13:Verilog HDL: Finite State Machine

Lecture 30           Finite State Machine

Quiz 11 Knowledge Check - Finite State Machine

14:Summary - Verilog HDL

Lecture 31           Summary

15:Verilog HDL : Labs

Lecture 32           Instructions - Verilog Labs

Lecture 33           Verilog Lab Manual

Lecture 34           Download the Verilog Labs Folder

Lecture 35           EDA Tools - Installation Guide

Lecture 36           EDA Tools - User Guide

Lecture 37           Solution to Lab 1

Lecture 38           Solution to Lab 2

Lecture 39           Solution to Lab 3

Lecture 40           Solution to Lab 4

Lecture 41           Solution to Lab 5

Lecture 42           Solution to Lab 6

Lecture 43           Solutions - Verilog Labs

16:Project: RISC-V RV32I Multi stage pipeline processor RTL Design

Lecture 44           The RISC-V Instruction Set Manual

Lecture 45           MSRV32I Core Design Specification

Lecture 46           RISC-V RV32I - Quick Reference Guide for Instrcutions