SystemVerilog for Verification

1:Verification Methodology Overview

Lecture 1Introduction to Verification Methodology

Lecture 2Verification Process

Lecture 3Reusable TB

Lecture 4Verification Environment Architecture

Lecture 5Constraint Random Coverage Driven Verification

Lecture 6Verification Methodologies & Summary

Quiz 1Knowledge Check

2:SystemVerilog Reference Book

Lecture 7SystemVerilog Reference Book

Lecture 8SystemVerilog - Quick Reference Guide

3:SystemVerilog Language Concepts

Lecture 9SV Concepts Agenda

Lecture 10SV Overview

Lecture 11SV Transactions

Lecture 12SV Interface

Lecture 13SV Virtual Interface

Lecture 14SV OOP

Lecture 15SV Randomization & Functional Coverage

Lecture 16SV TB Architecture

Quiz 2Knowledge Check - SV Concepts

4:SystemVerilog Datatypes

Lecture 17SystemVerilog Introduction & Logic Data Type

Lecture 18SV Data Types - 2 State, Struct & Enum

Lecture 19SV Data Types - Strings,Packages & Summary

Quiz 3Knowledge Check - Data Types

5:SystemVerilog Memories

Lecture 20SV Memories - Introduction, Packed and Multi Dimensional Arrays

Lecture 21SV Memories - Dynamic Arrays & Queues

Lecture 22SV Memories - Associative Arrays, Array Methods & Summary

Quiz 4Knowledge Check - Memories

6:SystemVerilog Tasks & Functions

Lecture 23SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task

Lecture 24SV Tasks & Functions - Pass by value & ref and Summary

Quiz 5Knowledge Check - Tasks & Functions

7:SystemVerilog Interfaces

Lecture 25SV Interfaces - Introduction & Verilog ports Vs SV Interface

Lecture 26SV Interfaces - Modports & Clocking Block

Lecture 27SV Interfaces - Examples & Summary

Quiz 6Knowledge Check - Interfaces

8:SystemVerilog Object Oriented Programming - Basics

Lecture 28SV OOP - Introduction, Class Data Type & Objects

Lecture 29SV OOP - Constructor, Null Object, Object assignments and copy

Lecture 30SV OOP - Shallow Vs Deep Copy & Summary

Quiz 7Knowledge Check - OOP Basics

9:SystemVerilog Object Oriented Programming - Advanced

Lecture 31SV OOP - Introduction, Inheritance & Super

Lecture 32SV OOP - Static properties & methods and Pass by ref

Lecture 33SV OOP - Polymorphism, $cast, Virtual & Parametrised classes, Summary

Quiz 8Knowledge Check - OOP Advanced

10:SystemVerilog Randomization

Lecture 34SV Randomization - Introduction, rand and randc

Lecture 35SV Randomization - Randomize(), Pre and Post randomize & Constraints

Lecture 36SV Randomization - Set Membership, Constraints & Summary

Quiz 9Knowledge Check - Randomization

11:SystemVerilog Threads

Lecture 37SV Threads, Events, Mailbox and Semaphores

Quiz 10Knowledge Check - Threads & Mailboxes

12:SystemVerilog Virtual Interface

Lecture 38SV Virtual Interface - Introduction, Implementation & Examples

Quiz 11Knowledge Check - VIF

13:SystemVerilog Functional Coverage

Lecture 39SV Functional Coverage - Introduction & CRCDV

Lecture 40SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary

Quiz 12Knowledge Check - Functional Coverage

14:Case Study 1 : Dual Port RAM - SystemVerilog TB

Lecture 41Verification Plan

Lecture 42Testbench Architecture and Verification Flow

Lecture 43Transaction and Generator

Lecture 44Interface and Drivers

Lecture 45Monitors

Lecture 46Scoreboard and Reference Model

Lecture 47Environment and Testcases

15:Case Study 2 : Maven SoC - SystemVerilog TB

Lecture 48Maven SoC SystemVerilog Verification Environment

16:SystemVerilog Labs

Lecture 49SV lab Manual

Lecture 50Makefile Usage

Lecture 51Lab 1 Solution : Data Types

Lecture 52Lab 2 Solution : Interfaces

Lecture 53Lab 3 Solution : OOP Basics

Lecture 54Lab 4 Solution : Advanced OOP

Lecture 55Lab 5 Solution : Randomization

Lecture 56Lab 6 Solution : Threads, Mailbox & Semaphores

Lecture 57Lab 7 Solution : Transaction

Lecture 58Lab 8 Solution : Transactors

Lecture 59Lab 9 Solution : Scoreboard & Reference Model

Lecture 60Lab 10 Solution : Environment & Testcases

17:SystemVerilog Assertions SVA : Reference Book

Lecture 61SVA Reference Book

18:SVA : Introduction & Types of Assertions

Lecture 62What are Assertions?

Lecture 63Necessity of using SystemVerilog Assertions

Lecture 64Types of Assertions

Quiz 13SVA - Knowledge Check - 1

19:SVA : Building Blocks, System Functions

Lecture 65SVA Building Blocks

Lecture 66System Functions

Quiz 14SVA - Knowledge Check - 2

20:SVA : Writing Sequences and Implication Operators

Lecture 67How to write sequences?

Lecture 68Implication Operators

Lecture 69Exercise based on Implication Operators and Timing Windows

Quiz 15SVA - Knowledge Check - 3

21:SVA : Repetition Operators and Sequence Composition

Lecture 70Repetition Operators

Lecture 71Sequence Composition

Lecture 72Methods for Sequences

Quiz 16SVA - Knowledge Check - 4

22:SVA : Miscellaneous Concepts and Connecting Assertions to DUT

Lecture 73Miscellaneous Concepts in SVA

Lecture 74Connecting Assertions to DUT

Quiz 17SVA - Knowledge Check - 5

23:SVA Case Study

Lecture 75Alarm Clock Project Specification

Lecture 76Explanation to Project Specification

Lecture 77Solution Codes - Verilog Pilot Project

24:SVA Labs

Lecture 78SVA Lab Manual

Lecture 79SVA Lab Solution

25:SystemVerilog HVL - Module Test

Quiz 18SystemVerilog HVL - Module Test

Quiz 19SystemVerilog - Practical Test