VHDL

VHDL Overview and Concepts

Levels of Abstraction

Entity, Architecture

Data Types and declaration

Enumerated Data Types

Relational, Logical, Arithmetic Operators

Signal and Variables, Constants

Process Statement

Concurrent Statements

When-else, With-select

Sequential Statement

If-then-else, Case

Slicing and Concatenation

Loop Statements

Delta Delay Concept

Arrays, Memory Modeling, FSM

Writing Procedures

Writing Functions

Behavioral / RTL Coding

Operator Overloading

Structural Coding

Component declarations and instantiations

Generate Statement

Configuration Block

Libraries, Standard packages

Local and Global Declarations

Package, Package body

Writing Test Benches

Assertion based verification

Files read and write operations

Code for complex FPGA and ASICs

Generics and Generic maps