VLSI SoC Design using Verilog HDL

1:VLSI Introduction

Lecture 1Why VLSI ?

Lecture 2Semiconductor Industry Overview

2:SoC Design

Lecture 3Smart Phone SoC

Lecture 4System On Chip Design Architecture and Methodology

3:ASIC Vs FPGA

Lecture 5ASIC Vs FPGA

4:VLSI Design Flow

Lecture 6VLSI Front-End Design Flow Part I

Lecture 7VLSI Front-End Design Flow Part II

Lecture 8VLSI Back-End Design Flow

5:Knowledge Check

Quiz 1Knowledge Check - VLSI SoC Design

6:Verilog HDL

Lecture 9Setting Expectations - Course Agenda

Lecture 10Introduction to Verilog HDL

Quiz 2Knowledge Check - Introduction to Verilog HDL

7:Data Types

Lecture 11Data Types

Quiz 3Knowledge Check - Data Types

8:Verilog Operators

Lecture 12Verilog Operators

Quiz 4Knowledge Check - Verilog Operators

9:Advanced Verilog for Verification

Lecture 13Advance Verilog for Verification

Quiz 5Knowledge Check - Advanced Verilog for Verification

10:Assignments

Lecture 14Assignments

Quiz 6Knowledge Check - Assignments

11:Structured Procedures

Lecture 15Structured Procedures

Quiz 7Knowledge Check - Structured Procedures

12:Synthesis Coding Style

Lecture 16Synthesis Coding Style

Quiz 8Knowledge Check - Synthesis Coding Style

13:Finite State Machine

Lecture 17Finite State Machine

Quiz 9Knowledge Check - Finite State Machine

14:Summary - Verilog HDL

Lecture 18Summary

15:Reference Material

Lecture 19Verilog HDL Reference Book

16:Verilog Labs

Lecture 20Instructions - Verilog Labs

Lecture 21Verilog Lab Manual

Lecture 22Download the Verilog Labs Folder

Lecture 23EDA Tools - Installation Guide

Lecture 24EDA Tools - User Guide

Lecture 25Solution to Lab 1

Lecture 26Solution to Lab 2

Lecture 27Solution to Lab 3

Lecture 28Solution to Lab 4

Lecture 29Solution to Lab 5

Lecture 30Solution to Lab 6

Lecture 31Solutions - Verilog Labs