8086 PIN DIAGRAM – PIN DESCRIPTION

8086  PIN DIAGRAM-PIN DESCRIPTION:

Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V d.c. supply for its operation. The 8086 uses 20-line- address bus.  It uses a 16-line data bus. The 20 lines of the address bus operate in multiplexed mode. The 16-low order address bus lines are multiplexed with data and 4 high-order address bus lines are multiplexed with status signals. The pin diagram of Intel 8086 is shown in Fig.4.  

AD₀-AD₁₅ (Bidirectional):  Address/Data bus. These are low order address bus. They are multiplexed with data. When AD lines are used to transmit memory address the symbol A is used instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol

D is used in place of AD, for example D₀-D₇, D₈-D₁₅ or D₀-D₁₅. 

A₁₆-A₁₉ (Output): High order addresses bus. These are multiplexed with status signals.

 8086 Pin diagram  

A₁₆/S₃, A₁₇/S₄, A₁₈/S₅, A₁₉/S₆: The specified address lines are multiplexed with corresponding status signals.

BHE (Active Low)/S₇ (Output):  Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.

RD (Read) (Active Low): The signal is used for read operation. It is an output signal. It is active when low.

READY: This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. The signal is active high.

INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized.

NMI (Input) –NON-MASKABLE INTERRUPT: It is an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not mask able internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.  INTA: INTA: Interrupt acknowledges.  It is active   LOW during T₂, T ₃ and T _w of each interrupt acknowledge cycle.

 MN/ MX MINIMUM / MAXIMUM: This pin signal indicates what mode the processor is to operate in. 

RQ/GT RQ/GT0: REQUEST/GRANT: These pins are used by other local bus masters to force the processor to release the local bus at the end of the processor's current bus cycle. Each pin is bidirectional with RQ/GT having higher priority than RQ /GT₁. 

LOCK:  It’s an active low pin. It indicates that other system bus masters are not to allowed to gain control of the system bus while LOCK is active LOW. The LOCK signal   remains active until the completion of the next instruction.  

TEST: This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock.

CLK- Clock Input: The clock input provides the basic timing for processor operation and bus control activity. It’s an asymmetric square wave with 33% duty cycle.

RESET (Input)   :  RESET: causes the processor to immediately terminate its present activity.

The signal must be active HIGH for at least four clock cycles.

 Vcc – Power Supply ( +5V D.C.) 

GND – Ground

DT/R :  DATA TRANSMIT/RECEIVE:  This pin is needed in minimum system that desires to  use an 8286/8287 data bus transceiver. It is used to control the direction of data flow through the transceiver.

DEN: DATA ENABLE This pin is provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles.

 HOLD/HOLDA: HOLD indicates that another master is requesting a local bus. This is an active HIGH. The processor receiving the `hold'' request will issue HLDA (HIGH) as an acknowledgement in the middle of a T ₄ or T ₁ clock cycle.