8255: (Programmable Peripheral Interface)

      In previous lectures we have discussed how to interface I/O devices with the system bus. If an input device, for example 8-toggle switches, are to be interfaced with the processor, they can be connected to data bus through 8-bit tri-state bus buffer. The status of switches can be read using IN PORT instruction in isolated I/O mode. The buffer is enabled during the execution of 3^rd machine cycle (IORDMC) when IO/M =1, RD =0 and address of the device is available on address bus. Similarly, if an output device, for example 8-LEDs are to be interfaced, they can be connected to data bus using 8-bit latch. The 8-bit data can be sent to LEDs using OUT PORT instruction in isolated I/O mode. During the 3^rd machine cycle (IOWRMC), the latch is enabled when IO/M =1, WR =0 and address of the output device is available on address bus.

If the system is designed using buffer and latches to interface input and out devices, then in future, it is not possible to change any input device with the output device or vice-versa. In order to make it simpler, Intel has designed 8255A chip to interface I/O devices.

The Intel 8255A is a general purpose programmable I/O device designed for use with Intel microprocessors. It consists of three 8-bit bidirectional I/O ports (24 I/O lines) that can be configured to meet different system I/O needs. The three ports are designated as PORT A, PORT B and PORT C. Port A contains one 8-bit output latch/buffer and one 8-bit input buffer. Port B is same as PORT A or PORT B. However, PORT C is split into two parts- PORT C lower (PC₃-PC₀) and PORT C upper (PC₇-PC₄) by the control word. The four ports – two 8-bit PORTs and two 4-bit PORTs are divided in two groups Group A (PORT A and upper PORT C) Group B (PORT B and lower PORT C) for programming purpose. These two groups can be programmed in three different modes:

1. Mode-0

2. Mode-1

3. Mode-2

In the first mode, mode-0, each group may be programmed in either input mode or output mode (PORT A, PORT B, PORT C lower, PORT C upper). In mode-1, the second mode, each group may be programmed to have 8-lines of input or output (PORT A or PORT B) and of the remaining 4-lines (PORT C lower or PORT C upper) 3lines are used for handshaking and interrupt control signals. The third mode of operation, mode-2, is a bidirectional bus mode which uses 8lines (PORT A) only for a bidirectional bus and five lines (PORT C upper 4 lines and borrowing one line from PORT C lower) for handshaking and control signals. PORT A and PORT B have both input and output buffers and latches but PORT C has output latch and input buffer. 

Functional Description: 

This support chip is a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. It is programmed by the system software so that normally no external logic is necessary to interface peripheral devices or structures. 

 Data Bus Buffer:

It is a tri-state 8-bit buffer used to interface the chip to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. The data lines are connected to BDB of ????p.

 Read/Write and Logic Control:

The function of this block is to control the internal operation of the device and to control the transfer of data and control or status words. It accepts inputs from the CPU address and control buses and, in turn, issues command to both the control groups.  

CS (Chip Select):

A low on this input selects the chip and enables the communication between 8255A & the CPU. It is connected to the output of address decode circuitry to select the device when it is addressed. 

RD (Read): 

A low on this input enables the 8255A to send the data or status information to the CPU on the data bus.

WR (Write):

A low on this input pin enables the CPU to write data or control words into the 8255A.

  A₁, A₀ Port Select:

These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word registers. They are normally connected to the least significant bits of the address bus (A₀ and A₁).