Blended VLSI M5 Verilog HDL

1:Verilog HDL Reference Material

Lecture 1Verilog HDL - Quick Reference Guide

2:Introduction to Verilog HDL

Lecture 2Setting Expectations - Course Agenda

Lecture 3Introduction to Verilog HDL

Quiz 1Knowledge Check - Introduction to Verilog HDL

3:Data Types

Lecture 4Data Types

Quiz 2Knowledge Check - Data Types

4:Verilog Operators

Lecture 5Verilog Operators

Quiz 3Knowledge Check - Verilog Operators

5:Verilog for Verification

Lecture 6Verilog for Verification

Quiz 4Knowledge Check - Verilog for Verification

6:Assignments

Lecture 7Assignments

Quiz 5Knowledge Check - Assignments

7:Structured Procedures

Lecture 8Structured Procedures

Quiz 6Knowledge Check - Structured Procedures

8:Synthesis Coding Style

Lecture 9Synthesis Coding Style

Quiz 7Knowledge Check - Synthesis Coding Style

9:Finite State Machine

Lecture 10Finite State Machine

Quiz 8Knowledge Check - Finite State Machine

10:Compiler Directive

Lecture 11Compiler Directive

11:Summary

Lecture 12Verilog HDL Summary

Lecture 13Verilog RTL Coding Examples

12:Verilog Labs

Lecture 14Instructions - Verilog Labs

Lecture 15Verilog Lab Manual

Lecture 16Download the Verilog Labs Folder

Lecture 17EDA Tools - Installation Guide

Lecture 18EDA Tools - User Guide

Lecture 19Solution to Lab1

Lecture 20Solution to Lab 2

Lecture 21Solution to Lab 3

Lecture 22Solution to Lab 4

Lecture 23Solution to Lab 5

Lecture 24Solution to Lab 6

13:Verilog Assignments

Lecture 25Verilog Assignment - 1

Lecture 26Solution to Verilog Assignment - 1

Lecture 27Verilog Assignment - 2

Lecture 28Solution to Verilog Assignment - 2

Lecture 29Verilog Assignment - 3

Lecture 30Solution to Verilog Assignment - 3

Lecture 31Verilog Assignment - 4

Lecture 32Solution to Verilog Assignment - 4

Lecture 33Assignment - 5 (Structured Procedures)

Lecture 34Solution to Verilog Assignment 5

Lecture 35Assignment - 6(Finite state machines)

Lecture 36Solution to Verilog Assignment 6

14:Practise Test

Quiz 9Verilog Weekly Quiz 1 -

15:M5 - Verilog HDL - Module Test

Quiz 10M5 - Verilog HDL - Module Test

16:Router 1x3 RTL design

Lecture 37Router_1x3_design_document

Lecture 38Introduction to Router

Lecture 39Router Top Packet Structure

Lecture 40Input Output Protocol

Lecture 41Router Architecture