RISC-V ISA & RV32I RTL Design

1:RISC-V Instruction Set Architecture

Lecture 1Why RISC-V Processor?

Lecture 2RISC-V processor overview

Lecture 3RISC-V ISA Overview

Lecture 4RV32I – R Type Instruction

Lecture 5RV32I – I Type Instruction

Lecture 6RV32I – S and B Type Instructions

Lecture 7RV32I – J and U Type Instructions

Lecture 8RV32I – Assembly Programs and Summary

Quiz 1Knowledge Check - RISC-V Instruction Set Architecture

2:RISC-V RV32I Reference Guide

Lecture 9RISC-V RV32I Quick Reference Guide

3:RISC-V RV32I RTL Architecture Design

Lecture 10RISC-V Execution Stages and Flow

Lecture 11RISC-V Register File and RV32I Instructions Format

Lecture 12RV32I – R Type ALU Datapath

Lecture 13RV32I – I Type ALU Datapath

Lecture 14RV32I – S Type ALU Datapath - Load & Store

Lecture 15RV32I – B Type ALU Datapath

Lecture 16RV32I – J Type ALU Datapath – JAL & JALR

Lecture 17RV32I – U Type ALU Datapath and Summary

Quiz 2Knowledge Check - RISC-V RTL Architecture Design

4:RISC-V RV32I 5 Stage Pipelined RTL Design

Lecture 18CPU Performance and RISC-V 5 Stage Pipeline Overview

Lecture 19RISC-V 5 Stage Pipeline – Data Hazards & Design Approach

Lecture 20RISC-V 5 Stage Pipeline – Control Hazards & Design Approach

Quiz 3Knowledge Check - RISC-V RV32I 5 Stage Pipelined RTL Design