RISC-V RV32I RTL Verification using UVM

1:RISC-V Instruction Set Architecture

Lecture 1             Why RISC-V Processor?

Lecture 2             RISC-V processor overview

Lecture 3             RISC-V ISA Overview

Lecture 4             RV32I – R Type Instruction

Lecture 5             RV32I – I Type Instruction

Lecture 6             RV32I – S and B Type Instructions

Lecture 7             RV32I – J and U Type Instructions

Lecture 8             RV32I – Assembly Programs and Summary

Quiz 1    Knowledge Check - RISC-V Instruction Set Architecture

2:RISC-V RV32I Reference Guide

Lecture 9             RISC-V RV32I Quick Reference Guide

3:RISC-V RV32I Processor

Lecture 10           RISC-V Execution Stages and Flow

Lecture 11           RISC-V Register File and RV32I Instructions Format

Lecture 12           RV32I – R Type ALU Datapath

Lecture 13           RV32I – I Type ALU Datapath

Lecture 14           RV32I – S Type ALU Datapath - Load & Store

Lecture 15           RV32I – B Type ALU Datapath

Lecture 16           RV32I – J Type ALU Datapath – JAL & JALR

Lecture 17           RV32I – U Type ALU Datapath and Summary

Quiz 2    Knowledge Check

4:RISC-V RV32I 5 Stage Pipeline Processor

Lecture 18           CPU Performance and RISC-V 5 Stage Pipeline Overview

Lecture 19           RISC-V 5 Stage Pipeline – Data Hazards & Design Approach

Lecture 20           RISC-V 5 Stage Pipeline – Control Hazards & Design Approach

Quiz 3    Knowledge Check - RISC-V RV32I 5 Stage Pipelined RTL Design

5:Universal Verification Methodology Overview

Lecture 21           Introduction to UVM

Lecture 22           UVM Concepts

Lecture 23           UVM SoC TB

Lecture 24           UVM AHB UVC

Lecture 25           UVM SoC TB Examples

Quiz 4    Knowledge Check - Universal Verification Methodology Overview

6:UVM Reference Guide

Lecture 26           UVM - Quick Reference Guide

7:UVM TB Architecture and Base Class Hierarchy

Lecture 27           UVM Testbench Architecture

Lecture 28           UVM Base Class Hierarchy

Quiz 5    Knowledge Check - UVM TB Architecture and Base Class Hierarchy

8:UVM Factory

Lecture 29           UVM Factory - Importance of using factory

Lecture 30           UVM Factory - Registration Process

Lecture 31           UVM Factory - Create Method and Factory Overriding

Quiz 6    Knowledge Check - UVM Factory

9:UVM - Stimulus Modelling & Testbench Overview

Lecture 32           UVM Stimulus Modelling - Predefined Methods and Field Registration Process

Lecture 33           UVM Stimulus Modelling - Overriding the predefined do_* methods

Lecture 34           UVM - TB Overview

Quiz 7    Knowledge Check - UVM Stimulus Modelling & TB Overview

10:UVM Phases & Reporting Mechanism

Lecture 35           UVM Phases - Necessity of Phases & pre-run Phases

Lecture 36           UVM Phases - Run Phase, post-run Phases and Objection Mechanism

Lecture 37           UVM Reporting Mechanism

Quiz 8    Knowledge Check - UVM Phases & Reporting Mechanism

11:UVM TLM Ports and Configuration

Lecture 38           UVM TLM Ports - Blocking put and get ports

Lecture 39           UVM TLM Ports - TLM FIFO and Analysis Ports

Lecture 40           UVM Configuration - Introduction to Configuration Facility

Lecture 41           UVM Configuration - Configuration class and Configuration of Virtual Interface

Quiz 9    Knowledge Check - UVM TLM Ports and Configuration

12:UVM - Creating UVM Testbench Components

Lecture 42           Creating UVM TB Components - Sequencers & Drivers

Lecture 43           Creating UVM TB Components - Monitor, Agents, Env and Testcases

Quiz 10 Knowledge Check - UVM - Creating UVM Testbench Components

13:UVM Sequences

Lecture 44           UVM Sequences - Introduction and Sequence item flow

Lecture 45           UVM Sequences - Starting the sequences and Default Sequence

Quiz 11 Knowledge Check - UVM Sequences

14:UVM - Virtual Sequences & Virtual Sequencers

Lecture 46           UVM Virtual Sequences & Virtual Sequencers - Introduction

Lecture 47           UVM Virtual Sequences & Virtual Sequencers - implementation

Quiz 12 Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers

15:UVM Callbacks & Events

Lecture 48           UVM Callbacks

Lecture 49           UVM Events

Quiz 13 Knowledge Check - UVM Callbacks & Events

16:UVM - Creating Scoreboard

Lecture 50           UVM Creating Scoreboard

Quiz 14 Knowledge Check - UVM - Creating Scoreboard

17:UVM - Register Abstraction Layer

Lecture 51           UVM RAL - Intro & Definition of Register Block

Lecture 52           UVM RAL - Adapter, Predictor and Integration

Lecture 53           UVM RAL - Definition of Register Sequences

Quiz 15 Knowledge Check - UVM RAL

18:UVM Lab Setup guide - reference manuals

Lecture 54           UVM Labs User Guide

Lecture 55           VPN Configuration Guide

19:Linux Operating System

Lecture 56           Introduction to Linux Operating System

Lecture 57           'vi' Text Editor

20:UVM Labs

Lecture 58           UVM Lab Manual

Lecture 59           Lab1 Solution : Stimulus Modeling

Lecture 60           Lab2 Solution : Factory Overriding

Lecture 61           Lab3 Solution : UVM Phases

Lecture 62           Lab4 Solution : Creating UVM agent

Lecture 63           Lab5 Solution : UVM Sequences

Lecture 64           Lab6 Solution : Virtual Interface

Lecture 65           Lab7 Solution : Agent Integration

Lecture 66           Lab8 Solution : UVM Socreboard

Lecture 67           Lab9 Solution : SoC - UVM VE implementation

Lecture 68           Lab10 Solution : Coverage & Regression

21:Project: RISC-V RV32I Multi stage pipeline processor verification

Lecture 69           Project Specification