Universal Verification Methodology - UVM

1:Universal Verification Methodology Overview

Lecture 1Introduction to UVM

Lecture 2UVM Concepts

Lecture 3UVM SoC TB

Lecture 4UVM AHB UVC

Lecture 5UVM SoC TB Examples

Quiz 1Knowledge Check - Universal Verification Methodology Overview

2:UVM Reference Book

Lecture 6UVM Reference Book

Lecture 7UVM - Quick Reference Guide

3:UVM TB Architecture and Base Class Hierarchy

Lecture 8UVM Testbench Architecture

Lecture 9UVM Base Class Hierarchy

Quiz 2Knowledge Check - UVM TB Architecture and Base Class Hierarchy

4:UVM Factory

Lecture 10UVM Factory - Importance of using factory

Lecture 11UVM Factory - Registration Process

Lecture 12UVM Factory - Create Method and Factory Overriding

Quiz 3Knowledge Check - UVM Factory

5:UVM - Stimulus Modelling & Testbench Overview

Lecture 13UVM Stimulus Modelling - Predefined Methods and Field Registration Process

Lecture 14UVM Stimulus Modelling - Overriding the predefined do_* methods

Lecture 15UVM - TB Overview

Quiz 4Knowledge Check - UVM Stimulus Modelling & TB Overview

6:UVM Phases & Reporting Mechanism

Lecture 16UVM Phases - Necessity of Phases & pre-run Phases

Lecture 17UVM Phases - Run Phase, post-run Phases and Objection Mechanism

Lecture 18UVM Reporting Mechanism

Quiz 5Knowledge Check - UVM Phases & Reporting Mechanism

7:UVM TLM Ports and Configuration

Lecture 19UVM TLM Ports - Blocking put and get ports

Lecture 20UVM TLM Ports - TLM FIFO and Analysis Ports

Lecture 21UVM Configuration - Introduction to Configuration Facility

Lecture 22UVM Configuration - Configuration class and Configuration of Virtual Interface

Quiz 6Knowledge Check - UVM TLM Ports and Configuration

8:UVM - Creating UVM Testbench Components

Lecture 23Creating UVM TB Components - Sequencers & Drivers

Lecture 24Creating UVM TB Components - Monitor, Agents, Env and Testcases

Quiz 7Knowledge Check - UVM - Creating UVM Testbench Components

9:UVM Sequences

Lecture 25UVM Sequences - Introduction and Sequence item flow

Lecture 26UVM Sequences - Starting the sequences and Default Sequence

Quiz 8Knowledge Check - UVM Sequences

10:UVM - Virtual Sequences & Virtual Sequencers

Lecture 27UVM Virtual Sequences & Virtual Sequencers - Introduction

Lecture 28UVM Virtual Sequences & Virtual Sequencers - implementation

Quiz 9Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers

11:UVM Callbacks & Events

Lecture 29UVM Callbacks

Lecture 30UVM Events

Quiz 10Knowledge Check - UVM Callbacks & Events

12:UVM - Creating Scoreboard

Lecture 31UVM Creating Scoreboard

Quiz 11Knowledge Check - UVM - Creating Scoreboard

13:UVM - Register Abstraction Layer

Lecture 32UVM RAL - Intro & Definition of Register Block

Lecture 33UVM RAL - Adapter, Predictor and Integration

Lecture 34UVM RAL - Definition of Register Sequences

Quiz 12Knowledge Check - UVM RAL

14:UVM Labs

Lecture 35UVM Lab Manual

Lecture 36Makefile Usage

Lecture 37Introduction to UVM Labs

Lecture 38Lab1 Solution : Stimulus Modeling

Lecture 39Lab2 Solution : Factory Overriding

Lecture 40Lab3 Solution : UVM Phases

Lecture 41Lab4 Solution : Creating UVM agent

Lecture 42Lab5 Solution : UVM Sequences

Lecture 43Lab6 Solution : Virtual Interface

Lecture 44Lab7 Solution : Agent Integration

Lecture 45Lab8 Solution : UVM Socreboard

Lecture 46Lab9 Solution : SoC - UVM VE implementation

Lecture 47Lab10 Solution : Coverage & Regression

15:Universal Verification Methodology - Module Test

Quiz 13Universal Verification Methodology - Module Test

Quiz 14UVM - Practical Test