Real-Time Mission-Critical Systems Design

Real-Time Mission-Critical Systems Design training provided by University of Colorado

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Created by University of Colorado Staff Last updated Wed, 02-Mar-2022 English


Real-Time Mission-Critical Systems Design free videos and free material uploaded by University of Colorado Staff .

Syllabus / What will i learn?
  • 28th Feb, 2022

Device I/O interfaces and Drivers for Real-time Systems

This module covers RTES software to hardware interface using device abstraction and driver interfaces as well as system scaling.

Fault Tolerant Memory and Storage for Mission Critical Systems

This module covers use of key algorithms such as error correct codes, redundant arrays of devices, and use of flash file systems with persistent memory.

Solving performance and reliability defects in real-time systems

Service software implementation efficiency and optimization methods are covered so that computations can be completed by deadlines. Methods of profiling and tracing applications as well as the whole system are covered.

Difference between high availability and high reliability for hard and soft real-time systems

This module integrates fault tolerant and recovery methods with overall strategies for system level fault detection, isolation and recovery. Design with consideration of failure modes and effects analysis is covered along with redundancy management for high availability.



Curriculum for this course
0 Lessons 00:00:00 Hours
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Description

This course can also be taken for academic credit as ECEA 5317, part of CU Boulder’s Master of Science in Electrical Engineering degree.


Upon completion of this course the learner will know the difference between systems you can bet your life on (mission critical) and those which provide predictable response and quality of service (reliable). This will be achieved not only by study of design methods and patterns for mission critical systems, but also through implementation of soft real-time systems and comparison to hard real-time. Methods of verification to determine ability to meet mission critical as well as soft real-time requirements will be learned so that the learner can properly assess risk, reliability and impact of failure in real-time systems.


At the end of this course learners will be able to apply an architectural style (cyclic executive, RTOS, or embedded Linux) to more detailed design of a mission critical system, a soft real-time system, or a mixed hard and soft real-time system, including:

● Thorough understanding of hardware/software device interfaces and resource view for hardware abstraction layers (HAL, BSP)
● Design trade-offs with different real-time hardware architectures including single core, multi-core, hybrid-FPGA, GP-GPU, and DSP systems, with emphasis on multi-core
● Mission critical embedded systems architecture and key design elements ● Fault tolerant processing, memory, and I/O concepts

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