RISC-V ISA & RV32I RTL Architecture Design Training Provided by Maven Silicon Softech Pvt Ltd Training Institute in Bangalore
RISC-V ISA & RV32I RTL Architecture Design free videos and free material uploaded by Maven Silicon Softech Pvt Ltd Training Institute staff .
1:VLSI Introduction
Lecture 1 Why
VLSI ?
2:SoC Design
Lecture 2 Smart
Phone SoC
Lecture 3 System
On Chip Design Architecture and Methodology
3:ASIC Vs FPGA
Lecture 4 ASIC
Vs FPGA
4:VLSI Design Flow
Lecture 5 VLSI
Front-End Design Flow Part I
Lecture 6 VLSI
Front-End Design Flow Part II
Lecture 7 VLSI
Back-End Design Flow
5:Knowledge Check
Quiz 1 Knowledge
Check - VLSI SoC Design
6:Digital Electronics
Lecture 8 Introduction
to Digital Electronics
7:Number Systems and
Codes
Lecture 9 Number
Systems and Codes
Quiz 2 Knowledge
Check - Number Systems and Codes
8:Logic Circuits
Lecture 10 Logic
Circuits
Quiz 3 Knowledge
Check - Logic Circuits
9:Combinational
Circuits
Lecture 11 Combinational
Circuits - I
Quiz 4 Knowledge
Check - Combinational Circuits - I
Lecture 12 Combinational
Circuits - II
Quiz 5 Knowledge
Check - Combinational Circuits - II
10:Sequential Circuits
Lecture 13 Sequential
Circuits - I
Quiz 6 Knowledge
Check - Sequential Circuits - I
Lecture 14 Sequential
Circuits - II
Quiz 7 Knowledge
Check - Sequential Circuits - II
11:Finite State
Machines
Lecture 15 FSM
Quiz 8 Knowledge
Check - FSM
12:Memories
Lecture 16 Memories
Quiz 9 Knowledge
Check - Memories
13:STA : Introduction
Lecture 17 Why
& What is Timing Analysis?
Lecture 18 Types
of Timing Analysis
Lecture 19 False
Paths & Multi Cycle Paths
Lecture 20 STA
in Design Flow
Quiz 10 Knowledge Check
: STA - Introduction
14:STA: Clock
Lecture 21 Clock
- Part -1
Lecture 22 Clock
- Part - 2
Quiz 11 Knowledge Check
: STA - Clock
15:STA : Timing
Parameters
Lecture 23 Timing
Parameters in STA - Part-1
Lecture 24 Timing
Parameters in STA - Part-2
Lecture 25 Timing
Parameters in STA - Part-3
Quiz 12 Knowledge Check
: STA - Timing Parameters
16:STA: Timing
Analysis Procedure
Lecture 26 Timing
Analysis on Sequential Circuits - Part-1
Lecture 27 Timing
Analysis on Sequential Circuits - Part-2
Lecture 28 STA
Procedure
Quiz 13 Knowledge Check
: STA - Timing Analysis Procedure
17:STA : Techniques
to Improve Timing
Lecture 29 Different
Techniques to improve timing
Quiz 14 Knowledge Check
: STA - Techniques to improve timing
18: RISC-V
RV32I Reference Guide
Lecture 30 RISC-V
RV32I Quick Reference Guide
19:RISC-V Instruction
Set Architecture
Lecture 31 Why
RISC-V Processor?
Lecture 32 RISC-V
processor overview
Lecture 33 RISC-V
ISA Overview
Lecture 34 RV32I
– R Type Instruction
Lecture 35 RV32I
– I Type Instruction
Lecture 36 RV32I
– S and B Type Instructions
Lecture 37 RV32I
– J and U Type Instructions
Lecture 38 RV32I
– Assembly Programs and Summary
Quiz 15 Knowledge Check
- RISC-V Instruction Set Architecture
20:RISC-V RV32I RTL
Architecture Design
Lecture 39 RISC-V
Execution Stages and Flow
Lecture 40 RISC-V
Register File and RV32I Instructions Format
Lecture 41 RV32I
– R Type ALU Datapath
Lecture 42 RV32I
– I Type ALU Datapath
Lecture 43 RV32I
– S Type ALU Datapath - Load & Store
Lecture 44 RV32I
– B Type ALU Datapath
Lecture 45 RV32I
– J Type ALU Datapath – JAL & JALR
Lecture 46 RV32I
– U Type ALU Datapath and Summary
Quiz 16 Knowledge Check
- RISC-V RTL Architecture Design
21:RISC-V RV32I 5
Stage Pipelined RTL Design
Lecture 47 CPU
Performance and RISC-V 5 Stage Pipeline Overview
Lecture 48 RISC-V
5 Stage Pipeline – Data Hazards & Design Approach
Lecture 49 RISC-V 5 Stage Pipeline – Control Hazards & Design Approach
Quiz 17 Knowledge Check
- RISC-V RV32I 5 Stage Pipelined RTL Design
This RISC-V training course trains you extensively on the
RTL design using Digital Electronics which includes the concepts of
combinational, sequential, FSM logic designs and Memories. It is composed of
modules that explain the concepts of Logic Gates, Adder, Subtractor, Decoder, Encoder,
Multiplexer, Demultiplexer, Flipflops, Latches, Counters, Registers, Memories
and Finite state machine.
Also, the STA module explains the importance of timing
analysis, how to do the timing analysis on both combinational Logic Circuits
and Sequential Circuits and the different strategies that one can implement to
improve the speed of the logic circuits.
Finally, this course explains the RISC-V ISA, pipeline
RISC-V processor RTL design architecture and how to improve the processor
performance, exploring various pipeline architectures.
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