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Week 1: The CMOS Inverter construction and Voltage Transfer Characteristics
Week 2: Resistance and Capacitance and transient response.
Week 3: Dynamic, Short Circuit and Leakage power – Stacking Effect
Week 4: Combinational Circuit Design and capacitance
Week 5: Parasitic Delay, Logical Effort and Electrical Effort
Week 6: Gate sizing and Buffering
Week 7: Asymmetric gate, Skewed gates, Ratio’ed logic
Week 8: Dynamic Gates and Domino logic and Static Timing Analysis
Week 9: Sequential circuits and feedback. Various D flip flop circuits – Static and Dynamic
Week 10:Setup and Hold Time measurement. Timing analysis of latch/ flop based systems
Week 11:Adders – Mirror adder, Carry Skip adder, Carry Select adder, Square Root adder
Week 12:Multipliers – Signed and Unsigned arithmetic, Carry Save Multiplier implementation
This is a most fundamental Digital Circuit Design course for pursing a major in VLSI. We do not deal with any Verilog coding during this course and instead discuss transistor level circuit design concepts in great detail. Over learning objectives of this course are:Characterize the key delay quantities of a standard cellEvaluate power dissipated in a circuit (dynamic and leakage)Design a circuit to perform a certain functionality with specified speedIdentify the critical path of a combinational circuitConvert the combinational block to pipelined circuitCalculate the maximum (worst case) operating frequency of the designed circuitINTENDED AUDIENCE : Any student interested in Circuit Design as applied to VLSI DesignPREREQUISITES : A course on digital logic design is a must for doing this course. INDUSTRY SUPPORT : All VLSI Design companies<!--td {border: 1px solid #ccc;}br {mso-data-placement:same-cell;}-->
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